Assemblies of integrated circuits generally comprise at least two integrated circuits fabricated independently and then joined together by a system of electrical connections placed between the two integrated circuits. These electrical connections are generally fabricated on each of the two integrated circuits and then soldered during a melting step.
During fabrication of these assemblies, electrically conducting through-vias (also known as Through Silicon Vias or TSVs) may also be produced within at least one of the integrated circuits. These vias make it possible to produce assemblies in which the frontside of one integrated circuit is against the backside of another integrated circuit. Thus, in such assemblies, called face-to-back assemblies, the through-vias electrically connect the metal lines of one integrated circuit and the electrical connections placed between the two integrated circuits.
Moreover, in assemblies in which the frontside of one integrated circuit is against the frontside of another integrated circuit, called face-to-face assemblies, the through-vias serve, for example, for connecting the assembly to a printed circuit using the flip-chip process well known to those skilled in the art.
A conventional assembly of two integrated circuits has been shown in FIG. 1. In this figure, two integrated circuits 101 and 102 have been shown schematically.
The circuit IC1 comprises, conventionally, a silicon substrate SUB and a number of metal lines LM. The metal lines LM form a BEOL (Back End Of Line) system interconnection of between the components of the integrated circuits. To join the backside of the integrated circuit IC1 to the frontside of the integrated circuit IC2 (face-to-back assembly), an electrically conducting through-via TSV1 is produced within the integrated circuit IC1.
More precisely, the substrate SUB of the integrated circuit IC1 is firstly thinned, for example by a mechanical polishing step, and then a through-orifice ORI is formed on the backside of the integrated circuit IC1. This through-orifice ORI opens onto at least one metal line LM of the integrated circuit IC1.
An insulating layer ISO, for example of silicon dioxide SiO2, is then deposited on the walls of the orifice ORI and on the backside of the integrated circuit IC1. The orifice ORI may have an aspect ratio of for example around 2 or 3, i.e. for example a height of 120 microns for a width of 60 microns, giving an aspect ratio of 2.
An electrically conducting layer RDL1 is then deposited on the walls of the orifice ORI, on the insulating layer ISO, and partially on top of the backside of the integrated circuit IC1. This conducting layer, generally called a redistribution line, is in electrical contact with a metal line LM and extends on top of at least part of the backside of the first integrated circuit IC1. The conducting layer RDL1 comprises a copper layer deposited on a tantalum layer that promotes adhesion of the copper, the tantalum layer itself being deposited on a tantalum nitride layer for limiting the diffusion of copper into the silicon.
The formation of the conducting layer RDL1 is followed by a step of depositing a photoresist RES1. The photoresist RES1 does not fill the orifice ORI, and has a thickness of around 2 microns.
To form an electrical connection between the integrated circuit IC1 and the integrated circuit IC2, a cavity is formed within the photoresist RES1 by a photolithography step. This cavity opens onto the conducting layer RDL1.
A layer forming a copper diffusion barrier/tie layer is then deposited on the backside of the integrated circuit IC1. This tie layer is covered with a second photoresist in which a cavity opening onto the conducting layer RDL1 is formed by a photolithography step. A copper electroplating step then enables the cavity opening onto the conducting layer RDL1 to be filled and a copper pillar CUP1 to be formed. The second photoresist together with the first photoresist makes it possible to obtain a sufficient thickness that a copper pillar CUP1 of sufficient height can be formed.
The second photoresist and the copper tie layer are then removed. A conducting region RDL2, for example made of copper, is placed on the second integrated circuit IC2, on the frontside of the integrated circuit IC2, and a copper pillar CUP2 is then formed on this conducting region.
More precisely, the production of the copper pillar CUP2 is preceded by a passivation of the conducting region RDL2 by means of a layer of silicon nitride (Si3N4), and an opening is made in this silicon nitride layer at the position of the copper pillar CUP2 by means of a photolithography step and a copper barrier/tie layer is deposited.
To create an electrical contact between the two integrated circuits IC1 and IC2, a low-melting-point alloy SAC is placed on the copper pillar CUP2. The combination formed by the copper pillar CUP2 and the alloy SAC is commonly referred to as just a “Copper Pillar”. This combination may have a thickness of around 30 microns.
A layer of polymer resin WLUF (Wafer Level Under-Fill) is then deposited on the frontside of the integrated circuit IC2 so as to cover the copper pillar CUP2 and the alloy SAC. When assembling the two integrated circuits, the alloy SAC is soldered to the pillar CUP1 and the layer WLUF is cured during a soft bake and fills the space between the two integrated circuits IC1 and IC2.
The assembly obtained has, in particular, the drawback of a cavity being formed in the orifice ORI. This cavity may result in gas being encapsulated and may cause the assembly to fail. This cavity may also cause oxidation of the copper.
Furthermore, this method for assembling the integrated circuits IC1 and IC2 comprises a large number of steps, more particularly two photolithography steps for depositing the two photoresist layers, the deposition of a tie layer, the deposition of copper, the deposition of the alloy SAC and the deposition of the polymer layer WLUF.
Moreover, the use of the polymer layer WLUF has the drawback of using tall copper pillars CUP1 and CUP2, for example having a total height of 40 microns, i.e. 10 microns for the pillar CUP1 and 30 microns for the pillar CUP2/alloy SAC combination.